板载双66AK2H14处理器，DSP Core Subsystems (C66x CorePacs), Each With – Up to 1.2 GHz C66x Fixed/Floating-Point DSP Cores › 38.4 GMacs/Core for Fixed Point @ 1.2 GHz › 19.2 GFlops/Core for Floating Point @ 1.2 GHz – Memory › 32K Byte L1P Per CorePac › 32K Byte L1D Per CorePac › 1024K Byte Local L2 Per CorePac ARM Cortex™-A15 MPCore™ Processors Containing Four (66AK2H14/12) or Two (66AK2H06) ARM Cortex-A15 Cores – Up to 1.4-GHz Cortex-A15 Processor Core Speed – 4MB L2 Cache Memory Shared by All ARM CorePacs – Full Implementation of ARMv7-A Architecture Instruction Set – 32KB L1 Instruction Cache and Data Cache per Cortex-A15 Processor Core – AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low Latency Access to Shared MSMC SRAM
